7th IWCFTA

1 Assoc. Prof. Mustak E. Yalcin

Istanbul Technical University

Mustak E. Yalcin was born in Unye, Turkey, in 1971. In 1993, he obtained the degree in Electronics and Telecommunications Engineering from Istanbul Technical University (I.T.U.), Electrical and Electronic Engineering Faculty. In 1997, he received the Master degree in Electronics and Communications Engineering from I.T.U. Institute of Science and Technology. In 2004, he recieved the Ph.D. degree in Applied Sciences from the Katholieke Universiteit Leuven, Belgium. Between June 2004 and December 2004, he was a postdoctoral fellow at Katholieke Universiteit Leuven, Department of Electrical Engineering (ESAT)/SCD-SISTA. He was also a Visiting Research Fellow at The Institute for Nonlinear Science, University of California San Diego (UCSD) in 2009. He is currently an Associate Professor with Istanbul Technical University, Turkey. His research interests are mainly in the areas of the theory and application of neural networks and nonlinear systems. He is co-author of the book "Cellular Neural Networks, Multi-Scroll Chaos and Synchronization" (World Scientific).

Title : A Novel Chaotic Time-delay Sampled-data System and its Circuit Implementation
Abstract : Chaotic autonomous and non-autonomous systems require at least third-order and second-order continuous-time systems, respectively. However, a first-order continuous-time system with time-delay feedback can generate chaos. Although chaotic time-delay systems may be of smaller degree than the other types of systems, from the implementation point of view, the complexity of the time-delay block is the main drawback of these systems. In order to overcome this drawback, we have recently introduced a chaotic delay differential equation which includes binary time-delay feedback function. This function allows to use simplified digital circuitry to implement time-delay block. Modeling the chaotic system thus obtained yields a chaotic time-delay sampled-data system. In this talk, I will first introduce a chaotic time-delay and n-scroll chaotic attractors from the chaotic time-delay system [1,2] together with their circuit implementations. Then, the chaotic time-delay sampled-data system and its circuit implementation will be presented [3]. Furthermore, I will presented generalization of binary time-delay feedback function in order to obtain multiple attractors from the chaotic time-delay sampled-data system.
References:
[1] Yalcin M. E. and Ozoguz S., "n-Scroll chaotic attractors from a first-order time-delay differential equation," Chaos: An Interdisciplinary Journal of Nonlinear Science, vol. 17, no. 3, 033112, 2007, doi: 10.1063/1.2768403.
[2] Kilinc S., Yalcin M.E. and Ozoguz S. " Multi-scroll chaotic attractors from a hysteresis based time-delay differential equation," International Journal of Bifurcation and Chaos, vol. 20, no. 10, pp. 3275-3281, 2010, doi:10.1142/S0218127410027660.
[3] Yalcin M.E.,Yeniceri R. and Ozoguz S." A Chaotic Time-delay Sampled-data System and its Implementation," International Journal of Bifurcation and Chaos, Vol. 44, No 3, 2014, doi:10.1142/S0218127414500394.

Web site:http://www2.itu.edu.tr/~yalcinmust

2 Prof. Serdar Ozoguz

Istanbul Technical University

Serdar Ozoguz was born on March 21, 1968. He received his BSEE, MSEE and PhD degrees in Electronics Engineering from Istanbul Technical University in 1991, 1993 and 2000 respectively. Since 2009, he is working as a full professor in Istanbul Technical University. His research interests include analog circuit design, chaotic circuits and chaos applications. Serdar Ozoguz has become a recipient of the Young Scientist Award of the Scientific and Technical Research Council of Turkey (TUBITAK) in 2004 and the Outstanding Young Scientist Award of the Turkish Academy of Sciences in 2002. He also received Best Paper Award with his papers presented in European Conference on Circuit Theory and Design in 2005, in Proc. of Int. Conf. on Applied Electronics in 2008 and in 2010.

Title : True random number generators based on chaotic systems
Abstract : :As a result of increasing demand of electronic official transactions and digital signature applications, today, generation of good non-repeatable and non-predictable random number sequences is of increasing importance, even in typical digital communication equipments. Compact and fast random number generators can be implemented in standard CMOS-process using a chaotic-system driving a pseudo-random number generator. In this talk, after reviewed several approaches appeared in the literature in the last decade, we will consider and discuss a recently presented hardware random number generator.

3 Dr. Mattia Frasca

Department of Electrical, Electronic and Computer Science Engineering, University of Catania, Italy

Mattia Frasca was born in Siracusa, Italy, in 1976. He graduated in Electronics Engineering in 2000 and received the Ph.D. in Electronics and Automation Engineering in 2003, at the University of Catania, Italy. Currently, he is research associate (ricercatore a tempo determinato) at the University of Catania. His scientific interests include nonlinear systems and chaos, Cellular Neural Networks, memristors, complex systems and bio-inspired robotics. He is involved in many research projects and collaborations with industries and academic centres. He is referee for many international journals and conferences. He is associate editor of IEEE Trans. Circuits and Systems I (2012-14), Int. J. Bif. and Chaos and Chaos, Solitons and Fractals. He was in the organizing committee of the 10th Experimental Chaos Conference and co-chair of the 4th International Conference on Physics and Control. He is in the board of the Italian Society of Chaos and Complexity. He is coauthor of three research monographs (with World Scientific): one on locomotion control of bio-inspired robots, one on self-organizing systems and one on the Chua's Circuit. He published more than 200 papers on refereed international journals and international conference proceedings and is co-author of two international patents. He is IEEE Senior.

Title : Chaotic circuits and adaptive synapses based on HP memristors
Abstract : Starting from the physical model of the TiO2 memristor discovered in the HP model, a gallery of chaotic circuits based on this device will be discussed. It includes both autonomous and non-autonomous circuits displaying a variety of nonlinear dynamical behaviors, limit cycles, bifurcations, strange attractors and multistability. Recent results on the design of synapses based on this memristor and suited for adaptive consensus and synchronization of two or more units will also be illustrated.

Web site:http://www.dees.unict.it/mfrasca/home.html

4 Prof. Simin Yu

Guangdong University of Technology

Simin Yu received the B.Sc. degree in physics from Yunnan University, Kunming, China in 1983, the M.E. degree in communication and electronic systems, and the Ph.D. degree in nonlinear circuits and systems, both from the South China University of Technology, Guangzhou, China in 1996 and 2001, respectively. Currently, he is a Full Professor in the College of Automation, Guangdong University of Technology, Guangzhou, China. His research interests include chaos theory and applications, design and analysis of nonlinear circuits and systems, and electronic science and technology. He has published more than 60 SCI journal papers, receiving more than 900 non-self SCI citations, 3 academic books and 6 granted patents in the fields of chaos in electronic circuits and chaotic communications. He is serving as Editorial Board both for Mathematical Problems in Engineering and for Journal of Applied Mathematics since 2014. Prof. Yu received the National Natural Science Award from the Chinese Government (Second Prize, Place No. 3), the Outstanding Teacher Award from the Guangdong Provincial Government, and the Excellent Instructor Award of Guangdong Province Outstanding Ph.D. Theses, in 2012, respectively. He also received the Natural Science Award from the Chinese Education Ministry in 2007 (First Prize, Place No. 4), and the Science and Technology Award from the Guangdong Provincial Government in 2011 (Second Prize, Place No. 1).

Title : Theoretical design and FPGA-ARM-based implementation of real-time chaos-based color video encryption-decryption communication systems
Abstract :

Abstract：A systematic methodology is proposed for a real-time chaos-based color video encryption and decryption communication system design with FPGA-ARM-based realization, based on an integer-domain chaotic system (IDCS) using Verilog Hardware Description Language (Verilog HDL) and the standard QT cross-platform, respectively. Both theoretical analysis and experimental results validate the feasibility and reliability of the new system. In addition, the color video recordings of the FPGA-based hardware experimental results for both parameter matched and mismatched cases, as well as the ARM-based hardware experimental results for both key matched and mismatched cases can be viewed online.

In the FPGA-based realization, according to the principle of anti-control of dynamical systems, a 6-dimensional real-domain chaotic system is firstly designed. By an integer processing method, the corresponding IDCS is then developed. To that end, the proposed IDCS and Verilog HDL program are utilized to design a real-time chaos-based secure color video communication, for which a generalized design principle is derived, implemented on an FPGA hardware platform with XUP Virtex-II chip. Then, the security performance of the designed system is tested by using the NIST statistical test suite. Finally, the working of the designed system is demonstrated by hardware experiments.

In the ARM-based realization, an 8-dimensional discrete-time chaotic map-based system is constructed, which possesses the required property of 1-1 surjection in the integer range [0, N-1], where N denotes the numbers of frame pixels, suitable for position scrambling of each color video frame. Based on the ARM-embedded platform super4412 model with Cortex-A9 processor, together with the standard QT cross-platform, an integrated chaos map-based real-time secure color video communication system is designed, implemented and evaluated.

Simulation videos:

Key matched ARM-chaos-based video secure communication.mp4

Key mismatched ARM-chaos-based video secure communication.mp4

Parameter matched FPGA-chaos-based video secure communication.mp4

Parameter mismatched FPGA-chaos-based video secure communication.mp4

5 Prof. Shukai Duan

College of Electronics and Information Engineering, Southwest University, Chongqing 400715 China

1996.7-2000.6任西南师范大学物理系、电子信息工程系年级辅导员、团总支书记、党总支秘书。2005.7-2008.3任物理科学与技术学院、电子信息工程学院任教工党支部书记、评估办副主任。2005年05月, 荣获西南师范大学“第八届青年成才奖励基金”。2005年11月破格晋升为副教授。2008.4-2011.11任物理科学与技术学院、电子信息工程学院任副院长，分管本科教学、实验室管理、高职教学和学生工作。2010年6月晋升为教授。2011年11月，获得第三重庆市高等学校优秀人才支持计划支持。2011.12后任西南大学担任教务处副处长。从事电子、通信和计算机等方面的教学、科研和管理工作。主要研究方向为：智能信息处理、人工神经网络、非线性理论与电路、微纳米电子学、自适应控制、忆阻器（memristor）及忆阻系统(memristive system)、非易失性存储器等领域研究。先后承担国家自然科学基金等省部级以上科研项目20余项。在Physics Letters A、中国科学、Computers & Mathematics with Applications、International Journal of Control, Automation, and Systems、Abstract and Applied Analysis等国内外学术刊物上发表论文60 余篇，其中被SCI /EI收录30余篇，国家发明专利2项。应邀担任Journal of Circuits, Systems and Computers、Neuroquantology、Computers and Electrical Engineering、Nonlinear Analysis: Modelling and Control、中国物理（B辑）、物理学报、通信学报、计算机科学、中国科技论文在线、西南大学学报等二十多个期刊和国际会议审稿人。全国信息与电子学科研究生教育协会理事，国家自然科学基金同行评议专家，教育部科研基金和科技奖励评审专家，全国大学生电子设计竞赛重庆赛区组委会副主任，重庆市重大项目会评专家，重庆市工业产品质量安全风险预警专家，重庆市科技咨询专家，重庆市人工智能学会理事，IEEE和IEEE Computational Intelligence Society会员等。

Title : Memristor-based Chaotic Circuits and Chaotic Neural Networks with Applications
Abstract : Over the last two decades, chaos in engineering systems, such as nonlinear circuits, has experienced the striking changes from being simply a scientific curiosity to a promising subject with theoretical significance and practical applications. Since the well-known physical paradigm of Chua’s circuit system was initially proposed in 1983, chaotic systems have long been considered as a rich mechanism for signal design and generation, and shown their expansive potential applications to the fields of data encryption, secure communications, signal processing, etc.

With the progress of researches, purposefully generating or enhancing chaos turned out to be a dominant issue in many technological and engineering applications. And we all know chaos can neither occur in first- or second-order autonomous continuous-time systems, nor in first-order non-autonomous continuous-time systems. It can merely exist in three-order autonomous continuous-time systems, such as Chua’s circuit and three-cell autonomous cellular networks. Therefore, we designed an electronic analog of a novel four-dimensional continuous autonomous chaotic system and achieved satisfactorily in generating more complex chaotic signals as designed. However, with the increase of dimensions, the system became more and more complex and it was no longer simple to be implemented in conventional electronic circuitries.

Fortunately and surprisingly, it was found that if one takes time delays into consideration, even simple neural networks with two or three non-linear neurons have the ability to exhibit chaotic dynamical behaviors. This discovery impelled us propose a circuitry implementation of Liao’s chaotic delayed neuron model, where time delayed circuit unit and non-monotonously increasing transform circuit unit were provided in detail, and its effectiveness was verified mathematically. Moreover, we designed and investigated an innovative delayed chaotic neural model, in which a non-monotonously increasing transfer function was obtained and employed as the activation function. As a result, a beautiful symmetrical chaotic attractor, just like a delicious water caltrop, was shown amazingly in electronic implementation.

Meanwhile, motivated and inspired by the widely known fourth fundamental circuit element--the memristor, which was theoretically predicted by Chua in 1971 and physically realized by Hewlett-Packard Laboratory in 2008, we proposed several memristor-based chaotic circuits successively, including simple three-order oscillators and four-order chaos or hyperchaos generators. Varieties of attractor evolutions, for example, from single roll to multiple rolls associated with rich bifurcation phenomena have been presented as well. The proposed chaotic circuits not only would be widely used as delayed chaos generators, chaotic neuron circuit unit, even a cell for cellular neural network but also showed their valuable potential applications to communications and signal processing.

On the other hand, to mimic biological neuron and construct intelligent information proceeding system, chaotic neuron and chaotic neural network were explored and initially presented by Aihara in 1990. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit practically. In order to boost the research on chaotic neural network, memristor-based hybrid nanoscale CMOS technology is proposed and expected to revolutionize the digital and neuromorphic computation. The proposed memristive chaotic neural network has the following four prominent features: (1) Nanoscale memristors in the network can simplify the synaptic circuit immensely and enable the synaptic weights to update easily; (2) The network can successfully separate stored patterns from superimposed input; (3) The network can execute many-to-many associative memory; (4) The network can accomplish the successive learning. It can be predicted undoubtedly the proposed implementation scheme of this novel chaotic neural network with memristive neural synapses will provide a feasible solution to further development of chaotic neural networks.

6 Prof. Zhigang Zeng

College of Automation, Huazhong University of Science and Technology, Wuhan, China

曾志刚：男，华中科技大学自动化学院教授、博士生导师，国家杰出青年科学基金获得者，IEEE Senior Member，图像信息处理与智能控制教育部重点实验室主任。2003年6月在华中科技大学获系统分析与集成博士学位。曾在香港中文大学和中国科技大学从事博士后研究。也曾在University of Western Sydney，Texas A&M University at Qatar作为访问研究员从事学术研究。研究方向为非线性系统稳定性、计算智能等。曾获2010年教育部高等学校科学研究优秀成果奖自然科学奖一等奖；2008年湖北省自然科学奖一等奖；2013年国家科学技术进步奖二等奖。2006年入选教育部新世纪优秀人才支持计划。获得2011年度湖北省有突出贡献中青年专家称号。先后担任IEEE Transactions on Neural Networks； IEEE Transactions on Cybernetics；Neural Networks；Applied Soft Computing；Cognitive Computation；自动化学报等学术期刊的编委，担任ISNN 2010，ICIST 2011，IWACI 2011，ICIST 2012，ICACI 2012，ICONIP 2012，ISNN 2013，ICIST 2013，ICICIP 2014，ISNN 2014等国际学术会议的程序委员会主席。

Title : 忆阻网络的动力学行为理论研究
Abstract : 首先介绍一种新的电路元件：忆阻。其次介绍基于忆阻的具有记忆功能的网络系统。最后，对忆阻网络系统的渐近行为特性的研究进行了初步探讨。探讨了忆阻网络系统的一些研究方向，包括忆阻网络系统模拟大脑神经行为；忆阻网络系统的多稳定性；忆阻网络系统的同步等。